1. Field of Invention
This invention relates to the design and layout of semiconductor memory bit cells using design rules that are smaller than the standard logic design rules for a given process technology node in order to reduce area per bit and improve performance.
2. Prior Art
Prior art for many types of memory bit cells such as Content Addressable Memories (CAMs) and Register File Memories use bit cells laid out using the standard logic design rules for a given process technology node such as 28-nanometer. This has the advantage that the design rules are proven to produce high yield and good reliability so the memory bit cells constructed in compliance with these rules also will have high yield and good reliability.
Most semiconductor fabrication companies also invest significant development effort to develop bit cells for Static Random Access Memories (SRAMs) with tighter design rules in order to improve bit density and memory performance. Typically this requires extensive experimentation and optical-proximity and contour simulations to adequately model and control geometric proximity effects. This effort is worthwhile since most integrated circuits use large amounts of memory so there is a huge multiplier for bit-cell area savings.
This invention leverages the development effort expended on SRAM bit-cell optimization by applying the results of that effort to new bit cell types with new functionality compared with SRAM bit cells such as CAM and Register File Memories. This is accomplished by reusing the geometrical structures optimized for SRAMs including the bit cells themselves and edge-cell structures and strap cells.